An I/O device within a computer system periodically requests service from a microprocessor within the computer system. The I/O device generates a signal known as an interrupt request (IRQ) to obtain the microprocessor's service. The type of service required by the I/O device depends on the type of device and its current condition. For example, a keyboard interface circuit generates an interrupt request to inform the microprocessor that a key has been pressed on a computer keyboard. The microprocessor then responds by perforating an I/O read bus cycle to get the corresponding keyboard character.
In the case of each interrupt request, the microprocessor executes a program known as an interrupt service routine (ISR). Separate ISRs exist for each of the types of interrupt requests generated by various I/O devices within the computer system. Upon receipt of an interrupt request, the microprocessor temporarily suspends execution of the current program, saves the program state, and jumps to the ISR. Upon completion of the ISR, the microprocessor restores the program state and returns to the original program, beginning at the step where the program was interrupted.
Typically, microprocessors have only a few individual interrupt request inputs used to detect service requests by multiple I/O devices. Instead of being sent directly to the microprocessor, the interrupt request signals from the various of I/O devices are received by one or more devices known as a programmable interrupt controllers (PICs), which in turn produce an interrupt signal which is received by the microprocessor. One well-known example PIC is the Intel.RTM. 8259A interrupt controller. In response to receipt of an interrupt signal, the microprocessor executes interrupt acknowledge bus cycles which cause the PIC to prioritize the currently pending service requests and to provide an interrupt vector to the processor on the processor data bus. The processor uses the interrupt vector as an index into an interrupt descriptor table stored in main memory. The interrupt descriptor table provides the starting memory addresses of each ISR. The programming of the interrupt vectors into the PIC, and of the interrupt descriptor table and ISRs into main memory, is well known and is typically performed during computer system start-up/initialization.
FIG. 1 depicts a typical computer system architecture. A microprocessor 10, such as the Pentium.TM. processor, is connected to a CPU bus 12 which carries address, data and control signals. The CPU bus 12 is connected to a system controller 14, a DRAM controller 16, and a data path controller 26. The DRAM controller 16 accesses a main memory DRAM 18 via a memory address bus and a memory control bus 20, 22, respectively. The data portion of the CPU bus 12 is coupled with the main memory DRAM 18 by a memory data bus 24 and the data path controller 26. A cache memory SRAM 28 is connected to the CPU bus 12 and provides the processor 10 with high speed access to a subset of the information stored in the main memory DRAM 18.
The system controller 14 serves as a bridge circuit between the CPU bus 12 and a system bus, such as peripheral component interconnect (PCI) bus 30. One or more of a wide variety of PCI devices 32 could be connected to the PCI bus 30. Well-known examples include a VGA controller, a CD ROM drive circuitry module with SCSI controller, interface circuitry (such as a PCI-PCI bridge controller) coupling another bus system and associated devices to the PCI bus 30, and PCI expansion slots for future accommodation of other PCI devices not selected during the original design of the computer system.
The PCI bus 30 is coupled with an expansion bus, such as industry standard architecture (ISA) bus 34, by expansion bus interface circuitry including a PCI-ISA bridge circuit 36 and an interrupt controller 40. One or more of a wide variety of ISA devices 38 could be connected to the ISA bus 34. Well-known examples include a floppy disk drive circuitry module with DMA controller, a keyboard/mouse controller, and ISA expansion slots for future accommodation of other ISA devices not selected during the original design of the computer system.
The interrupt controller 40 receives interrupt requests (IRQs) from the PCI devices 32 and the ISA devices 38 and outputs the interrupt signal INTR to the processor 10. When an IRQ is detected by the interrupt controller 40, it asserts INTR and the processor 10 initiates interrupt acknowledge cycles on the CPU bus 12. In response, the system controller 14 acquires control of the PCI bus 30 and initiates a PCI interrupt acknowledge transaction. The interrupt controller 40 then drives the interrupt vector onto an address/data (A/D) portion of the PCI bus 30, and the system controller 14 reads the vector and terminates the PCI interrupt acknowledge transaction. In turn, the system controller 14 drives the interrupt vector onto the data portion of the CPU bus 12 and asserts a command signal BRDY# to the processor 10. The processor 10 then reads the interrupt vector and uses it to index into the interrupt descriptor table to get the starting memory address of the requisite interrupt service routine.
The interrupt controller 40 of FIG. 1 typically includes two or more PICs connected in the well-known master-slave cascade configuration. PICs such as the Intel.RTM. 8259A are primarily designed for single microprocessor systems and have no mechanism to direct interrupts to different processors within a multiple processor system. Additionally, computer systems having traditional interrupt controllers use precious processor data bus time to transfer interrupt vector information. Advanced programmable interrupt controllers (APICs) have been developed which, together with traditional interrupt controllers, better support multiple processor systems. APICs can direct an interrupt to a specified one or more of the processors within the system, and a separate dedicated interrupt controller communication (ICC) bus provides command and interrupt vector information. One well-known APIC implementation includes two separate modules--a local APIC module integrated with each of the processors and an I/O APIC module which receives I/O device interrupt requests and routes them to the local APIC modules. A well-known example of a local APIC module is that integrated in the Intel.RTM. Pentium.TM. P54C processor. The Intel.RTM. 82430HX chip set includes an I/O APIC module which is placed standalone on the ISA bus.
FIG. 2 depicts a typical multiple processor computer system architecture. In addition to those components described above in connection with FIG. 1, the multiple processor system includes an I/O APIC module 42 which communicates via an interrupt controller communication (ICC) bus 44 with a plurality of local APIC modules 46, each integrated in a corresponding one of a plurality of microprocessors 11. The I/O APIC module 42 receives IRQs from the ISA devices 38, from the PCI devices 32, and from the PCI-ISA bridge circuit 36. The I/O APIC module 42 includes redirection registers (not shown), each loaded with an interrupt number corresponding to a particular one of the IRQs received. The I/O APIC module 42 sends the interrupt number on the ICC bus 44 (a three wire bus, having a clock line and two serial data lines) to the local APIC modules 46. The I/O APIC module 42 addresses one or more of the local APIC modules 46 to handle the interrupt request, and the processors 11 communicate with each other and with the I/O APIC module 42 for ICC bus arbitration and task sharing. The interrupt controller 40 does not have a significant function in the multiple processor system of FIG. 2, since it is disabled when the computer operating system detects multiple processors. Those IRQs generated internal to the PCI-ISA bridge 36 are passed to the I/O APIC module 42 via a special interrupt request signal, as shown.
Although APICs better support multiple processor systems, there exist numerous deficiencies in current implementations. The I/O APIC module 42, as a standalone chip on the ISA bus 34, results in significantly increased pin and signal line complexity relative to a single microprocessor-based computer system, such as that shown in FIG. 1. While some implementations integrate an I/O APIC module with an interrupt controller in PCI-ISA bus interface circuitry, such systems will still be made obsolete by future elimination of expansion buses such as the ISA bus. No prior art APIC-based system provides ready adaptability to future computer system designs, while maintaining compatibility with existing bus architectures.